1. Technical Field
The invention relates generally to memory cells, and more specifically, to semiconductor non-volatile memory devices.
2. Background Art
In non-volatile memory devices, the placements of the floating polysilicon (floating gate) and control gate of a cell are critical for the proper operability of a non-volatile storage transistor device. That is, the floating gate is required to overlap an isolation structure of the cell, and the control gate must align with the floating gate to ensure the proper formation of the device.
As feature sizes are reduced to sub-micrometer dimensions to achieve higher packing densities of devices, several problems emerge. First, large steps in the control gate can cause processing problems. Typically, the control gate polysilicon is depositing on a non-planar area, and thus will go up and over the floating gate, creating a large step for the control gate. Hence, during subsequent processing, the step in the control gate may become sufficiently steep to either allow the formation of a spacer or cause breaks in the silicide, ultimately degrading the memory cell.
Second, the depth of focus of the lithography stepper becomes smaller. Thus, the different heights of different features generate a depth of field problem.
Finally, a problem known as the "bird's beak" problem occurs where the isolation structure tapers to the substrate in the source and drain regions. Such a taper results in an electrical width smaller than the mask dimensions.
It is evident that the profusion of different heights during processing and the several alignment steps prevent efficient use of advanced lithography processes and other processes to generate high packing densities of devices on a substrate, since the depth of field reduces with the smaller dimensions that are needed for scaling.
Solutions to some of these problems are found in the following U.S. Patents: U.S. Pat. No. 5,559,048, "Method of Making a Double Layered Floating Gate EPROM With Trench Isolation", issued September 1996 to Inoue; U.S. Pat. No. 5,173,436, "Method of Manufacturing an EEPROM With Trench-Isolated Bitlines", issued December 1992 to Gill et al.; and U.S. Pat. No. 5,091,326, "EPROM Element Employing Self-Aligning Process", issued February 1992 to Haskell. These patents disclose self-alignment methods to eliminate some of the problems with the floating gate alignment.
Although the aforementioned patents use self-alignment techniques, some of the techniques have complex processing, and cell size still may not be reduced. Furthermore, in some cases, the control gate still develops a step, affecting the quality of the cell.